Master Thesis - Learned Evidence Ranking - Asic Verification Quality and Debug Using AI ML

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"Learned Evidence Ranking for Failure Diagnosis and Automated Testbench Quality Assessment in UVM-Based ASIC Verification"

About this opportunity:

A modern ASIC verification testbench executes hundreds of thousands of events in a single test: it generates randomized stimulus, drives protocol transactions, compares results against reference models, and coordinates many cooperating components. Only a tiny fraction of this activity is ever written to a log a message exists only where an engineer happened to add one.

The consequence shows up at the worst possible moment. A single regression test can produce an 11 MB log, yet when that test fails, the evidence that actually explains the failure is often just a few hundred bytes buried inside it. Today an engineer finds that evidence by hand, reading through the log step by step. In one measured case it took close to 3.5 hours to isolate the root cause, which came down to a single error, a cluster of repeated warnings, and one numeric value. Multiply that across a large regression and failure diagnosis becomes one of the most expensive, least glamorous parts of chip verification.

This thesis asks whether that effort can be learned and automated. Over years of verification, engineers have resolved tens to hundreds of trouble reports, each one implicitly recording which events mattered for a given failure. That history is a labelled dataset. The goal is to build a system that learns, from this evidence, to rank the events in a failing test by how diagnostically relevant they are turning hours of manual log inspection into an automatically ranked shortlist. The same behavioral signal opens a second question: can we automatically score how good a testbench actually is, based on what it does at runtime rather than on manual review?

You will work with real production regression data from Ericsson's ASIC verification environment, bridging two fields that rarely meet: hardware verification and machine learning. The project spans the full pipeline, understanding the data, framing the learning problem, building and evaluating models, and measuring the result against what expert engineers actually decided.

What you will do

• Build a data-driven framework for automated failure diagnosis and testbench quality assessment.
• Capture and correlate relevant verification events beyond conventional UVM messages.
• Train and evaluate a model that ranks events by diagnostic relevance.
• Compare the results with expert engineer assessments and manual triage effort, using real production regression data from an Ericsson accelerator IP.
• Develop a prototype for auditable testbench quality scoring.
• Stretch goal (optional): explore whether failure patterns can be detected before an error appears.

While working on this thesis, you will gain:

• A rare combination of hardware verification and machine-learning skills, increasingly in demand across the semiconductor industry.

• End-to-end ML experience on real production data from raw data to rigorous evaluation.

• Insight into how large chips are verified and where the hardest problems lie.

• Mentorship from experienced verification engineers at Ericsson, with access to real tools and data.

The skills you bring

• Master´s student in electrical or computer engineering, computer science, embedded systems, or a similar field.
• Knowledge of computer architecture, ASIC design and RTL/HDL coding.
• Experience with SystemVerilog and testbench design; working knowledge of UVM is preferred.
• Scripting experience, preferably Tcl or Python, for EDA tools.
• Fundamentals of artificial intelligence and machine learning.
• Exposure to at least one AI/ML model architecture, from data preparation through evaluation.
• An analytical and research-oriented mindset.
• Interest in verification, observability and data-driven engineering.

Why join Ericsson?

At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world's toughest problems. You´ll be challenged, but you won't be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

What happens once you apply?

Primary country and city: Sweden (SE) || Stockholm

Req ID: 791543