Senior Principal CPU Architect - Microarchitecture X86 Risc - V C++ C

Senior Principal CPU Architect - Microarchitecture / x86 / RISC-V / C++ / C Join a global technology organisation researching and developing next-generation high-performance computing architectures and microarchitectural innovations. Operating at the forefront of semiconductor innovation, silicon design, and workload acceleration, the company is building foundational CPU architectures designed to power compute-intensive workloads from Generative AI to confidential computing systems. This principal-level individual contributor role offers the opportunity to lead long-term architectural pathfinding and shape the microarchitectural roadmap for future high-performance processors. The position combines ISA evolution, deep out-of-order pipeline execution, hardware-software co-design, cycle-accurate simulation, and performance-power-area optimization. This is an on-site position in Cambridge, UK. Role Overview You will take technical ownership of defining next-generation processor concepts years ahead of commercial silicon production on-site in Cambridge. Your responsibilities will span the entire architectural pathfinding lifecycle—from evaluating emerging AI and graph analytics workloads to designing advanced execution pipelines, refining memory hierarchies, developing cycle-accurate simulator platforms, and collaborating with toolchain teams to drive hardware-software co-design. Key Responsibilities

• Lead architectural pathfinding and formulate long-range microarchitectural roadmaps for high-performance CPU cores.
• Architect advanced microarchitecture concepts covering fetch/decode units, out-of-order execution, speculative execution, register renaming, and multi-level cache coherency.
• Define and evaluate new ISA capabilities, including specialized vector/matrix extensions, exception models, and confidential compute features.
• Profile emerging workloads (LLMs, Generative AI, graph processing) and convert software bottlenecks into microarchitectural requirements.
• Drive hardware-software co-design efforts alongside compiler, kernel, and system software engineering teams.
• Guide the construction and maintenance of cycle-accurate CPU simulation models using C++ and Python.
• Perform rigorous performance, power, and area (PPA) trade-off analysis using simulation traces and workload profiling tools. Required Experience
• Extensive background in high-performance CPU microarchitecture definition, execution pipelines, and cache/memory hierarchy design.
• Master's or PhD in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
• Deep mastery of out-of-order execution, branch prediction, memory consistency models, virtualisation, and cache coherency protocols.
• Proven experience building, extending, and utilizing cycle-accurate CPU simulators (C, C++, Python) for microarchitectural exploration.
• Strong background in workload profiling, performance trace analysis, and metrics evaluation using tools such as Perf, VTune, or SimPoints.
• Preferred: Track record of bringing multiple high-performance CPU designs from concept through silicon tape-out.
• Preferred: Deep knowledge of x86, Arm, or RISC-V architectures, or active contributions to open ISA communities, LLVM, or GCC.
• Preferred: Exposure to advanced semiconductor packaging technologies, including chiplets and 3D stacking.